IRIS project

The general objective of the IRIS project is to develop a new family of Read Out Integrated Circuits (ROICs) for uncooled MWIR high-speed imagers with resolutions above 340×220 pixels.

PROJECT TITLE: IRIS project
START DATE: 01/09/2022
END DATE: 30/06/2026
PROJECT TITLE:  InfraRed Integrated Sensor for high-speed imagers – IRIS

PROJECT PARTNERS:
Coordinator:  NEW INFRARED TECHNOLOGIES SL
Partner: INSTITUTO DE MICROELECTRONICA DE BARCELONA – CENTRO NACIONAL DE MICROELECTRONICA (IMB-CNM)

IRIS Project Summary

The general objective of the IRIS project is to develop a new family of Read Out Integrated Circuits (ROICs) for uncooled MWIR high-speed imagers with resolutions above 340×220 pixels.

In particular, the project shall focus in identifying and developing all the technological bricks necessary for obtaining a ready-to-industrialize IRIS implementation that reduces the current size of the 50-µm pixel pitch and it improves the other performance figures in terms of power consumption, responsivity, speed and noise.

For this purpose, the advanced architectural and functional approaches of  Figure 3 are proposed, where the IRIS imager is built from a modular array of Digital Pixel Sensor (DPS) cells.

Each PbSe active pixel incorporates its own CMOS read-out circuit consisting on a custom analog-to-digital converter (ADC). In consequence, the tradeoff between frame rate and image quality can be improved, since the equivalent noise bandwidth is strongly reduced thanks to the massive parallel data conversion at the focal plane level, and inter-pixel crosstalk is also minimized due to the digital array communications.

In order to keep a low DPS pitch size and to achieve sub-frame latencies, the proposed in-pixel ADC is implemented according to a custom Integrate-and-Fire (IAF) modulator, which employs a highly linear soft-reset integrator frontend mechanism already developed by IMB-CNM, combined with a local digital subcounter of small capacity.

The asynchronous operation of the in-pixel ADC allows to generate low-latency events that can be already transferred to the acquisition system before completing the next image frame. The real-time processing of these intra-frame events should allow the early detection of specific image features for each application at reduced power and bandwidth costs. Moreover, the proposed frame-less operation is still compatible with classic read-out systems, as the IRIS ROIC is capable of collecting all image residuals in the pixel counters to properly compose a high-resolution frame at any time it is required by the application.

The general objective of the IRIS project is to develop a new family of Read Out Integrated Circuits (ROICs) for uncooled MWIR high-speed imagers with resolutions above 340×220 pixels. In particular, the project shall focus in identifying and developing all the technological bricks necessary for obtaining a ready-to-industrialize IRIS implementation that reduces the current size of the 50-µm pixel pitch and it improves the other performance figures in terms of power consumption, responsivity, speed and noise.